IBIS Macromodel Task Group Meeting date: 28 June 2022 Members (asterisk for those attending): Achronix Semiconductor: Hansel Dsilva Amazon: John Yan ANSYS: * Curtis Clark * Wei-hsing Huang Cadence Design Systems: Ambrish Varma Jared James Google: Zhiping Yang Intel: Michael Mirmak * Kinger Cai * Chi-te Chen Alaeddin Aydiner Keysight Technologies: * Fangyi Rao Majid Ahadi Dolatsara Ming Yan Radek Biernacki * Rui Yang Luminous Computing David Banas Marvell Steve Parker Mathworks (SiSoft): * Walter Katz Mike LaBonte Micron Technology: Randy Wolff * Justin Butterfield Missouri S&T Chulsoon Hwang SAE ITC Michael McNair Siemens EDA (Mentor): * Arpad Muranyi Teraspeed Labs: * Bob Ross Zuken USA: Lance Wang The meeting was led by Arpad Muranyi. Curtis Clark took the minutes. -------------------------------------------------------------------------------- Opens: - Arpad and Walter suggested we cancel the meeting on July 5th. The meeting on July 5th is cancelled (see below). ------------- Review of ARs: - None. -------------------------- Call for patent disclosure: - None. ------------------------- Review of Meeting Minutes: Arpad asked for any comments or corrections to the minutes of the June 21st meeting. Walter moved to approve the minutes. Bob seconded the motion. There were no objections. -------------- New Discussion: Cancelling the meeting on July 5th: Walter moved to cancel the meeting on July 5th. Curtis seconded. There were no objections. Supporting PI simulation in IBIS: Kinger reviewed a new presentation on his efforts to leverage existing EMD and IMS syntax while setting up a PI modeling proposal. He noted ongoing off-line discussions about the proposal. Kinger said he had largely agreed with the EMD modeling syntax Arpad and Walter asked him to consider. He said he liked it, but he had not been able to get agreement on whether we need a new keyword (to support the concept of grouping and sharing pins as references for ports). Walter said he still didn't understand the need for a new keyword and using groups of pins as the port references. He said if you're measuring or simulating to create the data for the Touchstone file, then you're going to be putting a differential probe on a VCC pin and a nearby GND pin to generate the port data. Since that's how you're generating the data, with the nearest GND pin/ball/pad as the reference, why do we need define groups of pins as the reference for ports? Kinger agreed that when setting up probe measurements you use one power and one nearby ground ball as your differential probe pair. However, when doing in- house design and optimization of a VRM, for example, they might combine the package and board data bases into one overall model and want to set up ports at that level. Similarly, when giving models to OEMs, chip vendors provide combined or abstracted electrical models to protect their IP. So, when distributing these package PI models to customers for their board designs, it's important to have the ability to define ports and reference groupings for the OEMs to interface to their board designs. We need to provide Touchstone data using these abstracted ports and the associated weighted AC sources, observation points, etc., provided by SPIM. Walter asked if Kinger could produce a small end-to-end example showing the problem to be solved, the simulation the customer would run, and the full syntax of the proposed IBIS PI model. He said Kinger's example slide showing multiple power and ground pins at the BGA level and the combined port definitions wasn't enough to understand the overall simulation flow. Kinger said that Chi-te was working out a step-by-step cookbook for creating models and could go over the details of the flow. He said they could provide accuracy data showing the correlation between simulations with their models and lab measurements. Kinger reviewed the Fast PI Design Target Definition, and he referred people to his 2020 EMC+SIPI IBIS Summit presentation. Bob asked if the goal was to embed these models in an .ibs file or have them exist in a stand-alone file. Kinger said he planned to follow the EMD approach and allow the flexibility to do it either way. Arpad asked if the plan was to enhance the existing EMD syntax or create an entirely new section. Kinger said he was still working with Walter and others off-line to decide. He said the issue is still about whether we need a new "signal group" vs. augmenting or combining with existing bus_labels. He said we might add a new PI model inside an EMD. Walter asked if this was for providing a PI model for the package. He said in that case it would be handled by interconnect model syntax (IMS), not EMD. Arpad reviewed the historical hierarchy: 1. Original IBIS - die model 2. Old fashioned RLC package 3. Now IBIS IMS supports Touchstone or IBIS-ISS models - now supports on-die interconnect from buffer terminals to pads - signals still restricted to 1-1 mapping from pin to pad 4. EMD - can support a board-level module like a DIMM, but it could also be used for a multi-chip module, in which case the EMD model is the package model for the multi-die component. Kinger said the primary focus now is on the package, and we might eventually move to the board level. However, this could be something of a black box model for which you define ports, a sensing port, etc., and these are the connections to the outside world. What's inside the model could be anything. Ultimately, we want general power distribution models not just chip package models. He said Zhiping and others are working on higher-level initiatives to standardize models for all components in the power delivery system. - Curtis: Motion to adjourn. - Walter: Second. - Arpad: Thank you all for joining. ------------- Next meeting: 12 July 2022 12:00pm PT ------------- IBIS Interconnect SPICE Wish List: 1) Simulator directives